1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which has a planarly dispersed charge storing means (for example, in a MONOS type or a MNOS type, charge traps in a nitride film, charge traps near the interface between a top insulating film and the nitride film, small particle conductors, etc.) in a gate insulating film between a channel forming region and a gate electrode in a memory transistor and is operated to electrically inject a charge into the charge storing means to store the same therein and to extract the same therefrom and a method of operating the device.
2. Description of the Related Art
Nonvolatile semiconductor memories offer promise as large capacity, small size data-storage media. Along with the recent spread of broadband information networks, however, write speeds equivalent to the transmission rates of the networks (for example, a carrier frequency of 100 MHZ) are being demanded. Therefore, nonvolatile memories are being required to have good scaling and be improved in write speed to one or more orders of magnitude higher than the conventional write speed of 100 xcexcs/cell.
As nonvolatile semiconductor memories, in addition to the floating gate (FG) types wherein the charge storing means (floating gate) that hold the charge is planarly formed, there are known MONOS (metal-oxide-nitride-oxide semiconductor) types wherein the charge storing means are planarly dispersed.
In an MONOS type nonvolatile semiconductor memory, since the carrier traps in the nitride film [SixNy (0 less than x less than 1, 0 less than y less than 1)] or on the interface between the top oxide film and the nitride film, which are the main charge-retaining bodies, are spatially (that is, in the planar direction and thickness direction) dispersed, the charge retention characteristic depends on not only the thickness of a tunnel insulating film (bottom insulating film), but also on the energy and spatial distribution of the charges captured by the carrier traps in the SixNy film.
When a leakage current path is locally generated in the tunnel insulating film, in an FG type, a large amount of charges easily leak out through the leakage path and the charge retention characteristic declines. On the other hand, in an MONOS type, since the charge storing means are spatially dispersed, only the charges near the leakage path will locally leak from it, therefore the charge retention characteristic of the entire memory device will not decline much.
As a result, in a MONOS type, the disadvantage of the degradation of the charge retention characteristic due to the reduction in thickness of the tunnel insulating film is not so serious as in an FG type. Accordingly, a MONOS type is superior to an FG type in scaling of a tunnel insulating film in a miniaturized memory transistor with an extremely small gate length.
Moreover, when a charge is locally injected into the plane of distribution of the planarly dispersed charge traps, the charge is held without diffusing in the plane and in the thickness direction like in an FG type memory.
To realize a miniaturized memory cell in a MONOS type nonvolatile semiconductor memory, it is important to improve the disturbance characteristic. Therefore, it is necessary to set the tunnel insulating film thicker than the normal thickness of 1.6 nm to 2.0 nm. When the tunnel insulating film is formed relatively thick, the write speed is in the range of 0.1 to 10 mo, which is still not sufficient.
In other words, in a conventional MONOS type nonvolatile semiconductor memory etc., to fully satisfy the requirements of reliability (for example, data retention, read disturbance, data rewrite, etc.), the write speed is limited to 100 xcexcs.
A high speed is possible if the write speed alone is considered, but sufficiently high reliability and low voltage cannot be achieved. For example, a source-side injection type MONOS transistor has been reported wherein the channel hot electrons (CHE) are injected from the source side (IEEE Electron Device Letter, 19, 1999, p. 153). In this source-side injection type MONOS transistor, in addition to the high operation voltages of 12V for write operations and 14V for erasure operations, the road disturbance, data rewrite, and other facets of reliability are not sufficient.
On the other hand, taking note of the fact that it is possible to inject a charge into part of dispersed charge traps area by the conventional CHE injection method, it has been reported that by independently writing binary data into the source and drain side of a charge storing means, it is possible to record 2 bits of data in one memory cell. For example, Extented Abstract of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 522-523, considers that by changing the direction of the voltage applied between the source and drain to write 2 bits of data by injecting CHE and, when reading data, applying a specified voltage with a direction reversed to that for writing, i.e., the so-called xe2x80x9creverse readxe2x80x9d method, correct reading of the 2 bits of data is possible even if the write time is short and the amount of the stored charge is small. Erasure is achieved by injecting hot holes.
By using this technique, it becomes possible to increase the write speed and largely reduce the cost per bit.
Furthermore, a split gate type MONOS nonvolatile memory able to record 2 bits in one cell was recently proposed (xe2x80x9cTwin MONOS Cell with Dual Control Gatesxe2x80x9d, 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123).
In this MONOS type nonvolatile memory, a split gate structure is employed to provide a control gate electrode in addition to the gate electrode so as to try to increase the write speed. The principle of this write method is basically channel hot electron injection. Since the impurity concentration around the drain is made relatively high comparing with that at the center of the channel, the injection efficiency of hot electrons is greatly improved.
However, in a conventional CHE injection type MONOS type or 2 bit/cell recordable MONOS type nonvolatile semiconductor memory, since electrons are accelerated in the channel to produce high energy electrons (hot electrons), it is necessary to apply a voltage larger than the 3.2 eV energy barrier of the oxide film, in practice a voltage of about 4.5V, between the source and drain. It is difficult to decrease this source-drain voltage. As a result, in a write operation, the punch-through effect becomes a restriction and good scaling of the gate length is difficult.
In addition, with the CHE injection method, since the efficiency of charge injection into the charge storing means is as low as 1xc3x9710xe2x88x926 to 1xc3x9710xe2x88x925, a write current of a few hundred xcexcA is needed. As a result, there is another problem that it is impossible to write in parallel a large number of memory cells simultaneously. To solve this problem, the write current has been reduced to 10 xcexcA per cell in the recently reported split gate type cells, but it is still difficult to write memory cells of more than 1 k bits in parallel because of the current restriction of the peripheral charge pump circuitry.
Moreover, with these three types of cells using the CHE injection method, because the write operation is performed with a current flowing in the channel of a memory transistor, it is impossible to simultaneously write at the source side and the drain side for the purpose of the aforesaid 2-bit data storage.
Furthermore, in the aforesaid 2-bit data recordable memory cells and split gate type memory cells, due to the necessity of local erasure, the method of erasure of injecting hot holes from the source or drain side utilizing FN tunneling or a band-to-band tunneling current has been employed. However, with this method, since passage of hot holes may cause deterioration of the oxide film, a decline in the reliability, in particular, the data rewrite, cannot be avoided.
Therefore, in a conventional MONOS type nonvolatile semiconductor memory, as long as the erasure is performed by hot hole injection, it is impossible to improve the performance by optimizing the thickness of the bottom oxide film.
An object of the present invention is to provide a MONOS type or other nonvolatile semiconductor memory device which basically operates by storing a charge in a planarly dispersed charge storing means such as a carrier trap, when injecting a charge into part of a region of distribution of the charge storing means to record a plurality of bits of data, it is possible to write at a high speed with an extremely low current while suppressing the punch-through effect and wherein the scaling of the gate length and the thickness of the gate insulating film is good, and a method of operating the device.
According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a channel forming region comprised of a first conductivity type semiconductor, two source and drain regions comprised of a second conductivity type semiconductor sandwiching the channel forming region between them, a gate insulating film provided on said channel forming region, a gate electrode provided on said gate insulating film, and a charge storing means which is formed in said gate insulating film dispersed in the plane facing said channel forming region and in the direction of thickness and is injected with hot electrons at the time of operation from said source and drain regions.
The hot electrons are those caused by a band-to-band tunneling current.
In the present invention, the number of recorded bits per cell may be either 2 bits per cell or 1 bit per cell.
In the former case, the gate insulating film may comprised of a storage region holding the hot electrons injected from said source and drain region and another region not injected by the hot electrons.
Alternatively, the gate insulating film may be comprised of two regions, referred to as first and second storage regions, holding the hot electrons injected from either the source region or the drain region and a third region between the first and the second regions into which the hot electrons are not injected.
A charge storing means is formed in the first and the second storage regions. The region of distribution of the charge storing means is spatially separated by the third region. Further, preferably, the first and the second storage regions are stacked film structures comprised of a number of films stacked together. The third region is a single layer of a dielectric.
Although a single gate electrode is also a possible choice, preferable the gate electrode comprises a first gate electrode formed on the first storage region, a second gate electrode formed on the second storage region, and a third gate electrode formed on the third region. The first, second, and third gate electrodes are spatially separated from each other. In order to simplify the fabrication process, the third electrode is formed on the single layer of dielectric. By stacking a number of films, a charge retaining film is formed in contact with the surfaces of the third electrode and the channel forming regions beside the third electrode. Due to formation of a gate electrode on the charge retaining film, the first and the second gate electrodes may consist of only the single gate electrode. In either case, the channel forming region consists of two channel forming regions of two memory transistors and a channel forming region of a control transistor between and in connection with the former two channel forming regions.
In more detail, a plurality of memory transistors each comprising a channel forming region, source and drain regions, gate insulating film, and gate electrode are arranged in the word line direction and in the bit line direction. In the memory transistors in the word line direction, the first and second gate electrodes are commonly connected through word lines, and in the memory transistors in the bit line direction, the third gate electrodes are commonly connected.
The gate electrode may also be a single one on the first and the second storage regions and the third region. In this case, two more gate electrodes are provided at the outer side of the first and the second storage regions spatially separated from the central gate electrode.
In the case of storing one bit per cell, a memory transistor comprising a channel forming region, source and drain regions, gate insulating film, and gate electrode may have a gate length shorter than or equal to the gate length when the region retaining hot electrons from one of the source and drain regions is merged or partially merged in the gate insulating film with the region retaining hot electrons from the other of the source and drain regions when hot electrons are injected from both the source and drain regions.
In the present nonvolatile semiconductor memory device, a separated source line type, virtual grounding type, or other NOR type cell array structure wherein a common line connected to one of the source and drain regions and a common line connected to another one of the source and drain regions can be controlled independently is preferable.
In a separated source line type, a common line connected to one of the source and drain regions is referred to as a first common line, while that connected to the other of the source and drain regions is referred to as a second common line.
In this case, the first and second common lines may have a hierarchical structure. In a so-called AND type cell array, memory transistors are connected in parallel to the first and the second sub-lines that are used as the inner interconnections in a memory block.
According to the second aspect of the present invention, there is provided a method of operating a nonvolatile semiconductor memory device comprising a channel forming region comprised of a first conductivity type semiconductor, source and drain regions comprised of a secondary conductivity type semiconductor with the channel forming region in between, a gate insulating film provided on the channel forming region and including inside it a charge storing means dispersed in a plane facing the channel forming region and thickness direction, and a gate electrode provided on the gate insulating film, the method comprises a stop of injecting hot electrons into the charge storing means from the source and drain regions when writing data to the device.
In the write operation, preferably hot electrons caused by the band-to-band tunneling current are injected into the charge storing means from the source and drain regions.
The operation methods are different for storing two bits in one cell and storing one bit in one cell.
In the case of storing two bits per cell, in a write operation, hot electrons may be injected into part of the region of distribution of the charge storing means. That is, hot electrons are injected into the first storage region from one of the source and drain regions, and independently, hot electrons are injected from another one of the source and drain regions into the second storage region separated from the first storage region. The gate insulating film may have a third region, between the first and the second storage regions, into which hot electrons are not injected. The region of distribution of the charge storing means is split spatially by the third region.
In the case of storing one bit per cell, the region retaining the hot electrons injected from one of the source and drain regions is merged or partially merged in the gate insulating film with the region retaining the hot electrons injected from the other of the source and drain regions. In more detail, a memory transistor comprising the channel forming region, source and drain regions, gate insulating film, and gate electrode has a gate length shorter than or equal to the merged gate length when merging or partial merging the two regions retaining the hot electrons.
In the present invention, in the write operation, a specified write voltage is applied between the source and drain regions and the gate electrodes.
As described above, in the case of a gate electrode consisting of the first, the second, the third gate electrodes, in a write operation of a memory cell array comprised of a plurality of memory transistors arranged in the word line direction and in the bit line direction, when writing data to one of the first and the second storage regions, the first and second gate electrodes of the other region are set in an electrically floating state or a voltage of 0V or of opposite polarity relative to the channel forming region is applied to the first or the second gate electrode of the other region.
Further, in a write operation of a memory cell array comprised of a plurality of memory transistors each comprising the channel forming region, source and drain regions, gate insulating film, and gate electrode arranged in the word line direction and in the bit line direction wherein the gate electrodes are commonly connected through word lines for every certain number of memory transistors in the word line direction, a voltage of 0V or of opposite polarity relative to the channel forming region is applied to the nonselected word lines not connected to the memory transistor in operation.
Moreover, in a write operation of a memory cell array comprised of a plurality of memory transistors each comprising the channel forming region, source and drain regions, gate insulating film, and gate electrode arranged in the word line direction and in the bit line direction wherein one of the source and drain regions is connected to a first common line and another one of the source and drain regions is connected to a second common line for every certain number of memory transistors in the bit line direction, a specified voltage is applied to the first or the second common line that is connected to the memory transistor in operation and a voltage of 0V or of opposite polarity relative to the specified voltage is applied to the first and the second common lines not connected to the memory transistor in operation.
In the present invention, even when the source or drain regions in one cell are separated from those in other cells in the word line direction (separated source line NOR type) or the source or drain regions in one cell are connected with the source or drain regions in other cells (virtual grounding type), if the first gate electrode on the first storage region and the second gate electrode on the second storage region are separated, memory cells connected to the same word line can be written simultaneously within one operation cycle.
That is, in the write operation of a memory cell array comprised of a plurality of memory transistors each comprising the channel forming region, source and drain regions, gate insulating film, and gate electrode arranged in the word line direction and in the bit line direction wherein the gate electrodes are commonly connected through word lines for every a certain number of memory transistors in the word line direction, in a write operation for all memory transistors connected to the same word line, a specified voltage is applied to all the source and drain regions corresponding to the first and the second storage regions into which hot electrons are injected, the source and drain regions corresponding to the first and the second storage regions into which hot electrons are not injected are set in an electrically floating state, a write voltage equal to a predetermined difference with the specified voltage applied to the source and drain regions is applied on the same word line, and all memory transistors connected to the same word line are written in parallel with one operation. Here, since the current required for writing is 1 nA per cell, which is sufficiently small comparing with that of the conventional CHE injection write method, it is possible to write in parallel more than 10 kilobits.
When reading data in the case of the aforesaid gate electrode consisting of the first, second, and third gate electrodes, a specified read drain voltage is applied between the two source and drain regions so that the storage region to be read becomes the source, a specified voltage is applied to the third gate electrode, and a specified read gate voltage of the same polarity with the voltage on the third gate electrode is applied to the first gate electrode and/or the second gate electrode.
In an erasure operation, the electrons which are injected from the source and drain regions and held by the charge storing means may be extracted to the source and drain region side by the direct tunneling effect or the Fowler-Nordheim tunneling effect.
Alternatively, the electrons which are injected from the source and drain regions and held at the two sides of a charge storing means in the channel direction may be extracted to the substrate side separately or simultaneously be the direct tunneling effect or the Fowler-Nordheim tunneling effect.
The present nonvolatile semiconductor memory device and the method for operating the same are suitable for example for devices where the charge storing means is formed and dispersed in a plane facing the channel forming region and in the thickness direction such as the MONOS type, small particle type having so-called nanocrystals or other small particle conductors, etc.
In the present nonvolatile semiconductor memory device and the method for operating the same, when writing two bits in one cell, hot electrons caused by a band-to-band tunneling current are injected into the charge storing means from the source and drain regions.
In more detail, if the source and drain regions are p-type impurity regions, application of a positive bias to the gate electrodes (first and second gate electrode) results in formation of an n-type inversion layer at the surfaces of the source and drain regions. Thus a high bias voltage is applied to the pn junction, and the energy bands in this inversion layer bend sharply. If the surface of the p-type impurity region is further deeply depleted, the effective bandgap decreases in this region. As a result, the band-to-band tunneling current occurs between the valence band and the conduction band. Electrons tunneling between the bands are accelerated by the electric field and become hot electrons. Their moments (magnitude and direction) are maintained and their energies are higher than the energy barrier of the oxide film, thus these electrons overcome the barrier and are locally injected into the charge storing means. In other words, if the voltage between one of the source and the drain regions and the first gate electrode is increased, hot electrons are injected and held in the first storage region of the charge storing means. If the voltage between another one of the source and the drain regions and the second gate electrode is increased, hot electrons are injected and held in the second storage region of the charge storing means. Since there is the third region into which hot electrons are not injected between the first and the second storage regions, charges corresponding to the two bits of data may be unambiguously distinguished.
In this process, hot electrons caused by the band-to-band tunneling current are injected into the charge storing means with an injection efficiency, for example, as high as 1xc3x9710xe2x88x922 to 1xc3x9710xe2x88x923. Thus, the write current per bit can be reduced to less than {fraction (1/10)}4 of that of the conventional CHE injection method. Therefore, it becomes possible to write in parallel more than 10 k memory cells, so the number of memory cells able to be written in parallel simultaneously (write bandwidth) increases. It also becomes possible for memory transistors connected to the same word line (one page) to be written with one operation.
In the method of writing two bits per cell described above, a write operation is performed at the source or the drain region which is not open and to which a write voltage is applied.
Therefore, in a read operation, a read drain voltage is applied so that the source or drain region to which the write voltage is applied becomes the source. The presence of a stored charge at the source or drain region that has a higher voltage does not influence the channel electric field much at all due to the pinch off effect, while the channel electric field changes influenced by the presence of a stored charge at the lower voltage side. Therefore, the threshold voltage of the memory transistor reflects the presence of a stored charge at the low voltage side.
As the most suitable memory transistor structure for writing 2 bits in one cell, for example, the gate insulating film including the charge storing means (carrier traps) is split in the channel direction into first and second storage regions located at the two sides of the gate insulating film and the third region between them is made an insulating film of a single material not containing a charge storing means. The third region at the center functions as a MOS type control transistor.
In this structure, by controlling the threshold voltage of the control transistor to within a certain range, reading can be performed with a constant current. In other words, assuming a p-channel type memory cell, when there is no control transistor, if the electrons are over-injected in the write operation and the threshold voltage of the memory transistor is largely decreased, the read current will fluctuate and much current will be wasted. However, in the present invention, because of the presence of the MOS type control transistor, if the threshold voltage of the memory transistor largely decreases and the read current starts to increase, the control transistor is cut off and functions as a limiter. As a result, in such a memory cell, the upper limit of the read current can be controlled by the threshold voltage of the control transistor and there is no unnecessary current consumption.
In the case of writing one bit in one cell, a write operation may be performed at both the source and the drain sides. In this case, although the charge injection areas from the source and drain regions are both localized, by optimizing the design of the source and drain regions so that the injection areas are sufficiently large, if the gate length is for example less than 100 nm, in the plane of distribution of the charge storing means, the charge injection area of one of the source and drain regions is at least partially merged near the center with the charge injection area of the other of the source and drain regions, therefore the charge is injected into substantially the entire area. Consequently, the threshold voltage of the memory transistor is largely decreased. In such a write operation, because the charge is injected into substantially the entire region of the plane of distribution of the charge storing means, the write time for obtaining a necessary change of the threshold voltage is, for example, less than 10 xcexcs or shortened by more than one order of magnitude comparing with a conventional memory cell that is able to be written in parallel.
When erasing data, for example, a positive voltage is applied to the source and drain regions and the stored charge at the source or drain side is extracted to the substrate side by using the direct tunneling effect or the FN tunneling effect. With either of the tunneling effects, it is possible to erase a block simultaneously.
In the present invention, because an operation the same as that of a split gate type memory cell is possible, over erasure or overwrite hardly even happens.